In recent years, as a solid-state image pickup device (an image sensor) alternative of a CCD, a CMOS (Complimentary Metal Oxide Semiconductor) image sensor attracts attention.
This is because the CMOS image sensor has overcome the following issues.
That is, producing CCD pixels needs a dedicated process, and operating the CCD pixels needs a plurality of power sources, further, it needs to combine a plurality of peripheral ICs to be operated.
On the contrary, the CMOS image sensor has overcome various problems of such CCD in which systems become extremely complex. Therefore, as described above, it attracts attention.
The CMOS image sensor uses the production process same as the one for an ordinary CMOS type integrated circuit, and can be operated by a single power source, further can have an mixture of an analog circuit and a logic circuit using the CMOS process, in the same chip.
For this reason, the CMOS image sensor has a plurality of great advantages, such as decreasing the number of peripheral ICs, or the like.
Mainstream of an output circuit of the CCD is a single channel (ch) output using a FD amplifier having a floating diffusion layer (FD).
On the contrary, the CMOS image sensor has a FD amplifier for each pixel, and mainstream of its output is a column-parallel output type for selecting one line from a pixel array, and for reading out in a column direction at once.
This is because the FD amplifier arranged inside of pixels hardly obtain efficient driving capability, causing necessity of decreasing data rate, and a parallel processing seems to be advantageous.
Such CMOS image sensor has been used as an image pick up device in a imaging apparatus, such as a digital camera, a camcorder, a surveillance camera, an onboard camera, or the like.
FIG. 1 is a diagram showing an example of an average structure of a CMOS image sensor that arranges pixels in a two-dimensional array.
A CMOS image sensor 10 in FIG. 1 is configured by a pixel array section 11, a vertical scan circuit (Vdec: pixel driving circuit) 12, and a column readout circuit (column processing circuit) 13.
The pixel array section 11 arranges a pixel circuit in a matrix of M rows and N columns.
The vertical scan circuit 12 controls an operation of pixel arranged in an arbitrary row in the pixel array section 11. The vertical scan circuit 12 controls pixels through control lines LRST, LTX, and LSEL.
The readout circuit 13 receives pixel row data controlled reading by the vertical scan circuit 12 through an output signal line LSGN, and transfers it to a signal processing circuit in the post-stage.
The readout circuit 13 includes a correlated double ampling circuit (CDS: Correlated Double Sampling) or an analog digital converter (ADC).
FIG. 2 is a diagram showing an example of pixel circuit of a CMOS image sensor configured by four transistors.
This pixel circuit 20 has, for example, a photoelectric conversion element 21 composed of photo diodes (PD) (hereinafter, referred to as simply PD, in some cases).
The pixel circuit 20 includes, for this one unit of the photoelectric conversion element 21, four transistors of a transfer transistor 22, a reset transistor 23, an amplifier transistor 24, and selection transistor 25, as active devices.
The photoelectric conversion element 21 photoelectrically converts incident lights into an amount of electric charge (as here, electron thereof) according to an amount of light thereof.
The transfer transistor 22 is connected between the photoelectric conversion element 21 and a floating diffusion FD hereinafter, referred to simply as FD, in some cases), and is to be given a transfer signal (a driving signal) TX to its gate (a transfer gate) through a transfer control line LTX.
Thus, the electron photoelectrically converted by the photoelectric conversion element 21 is transferred to the floating diffusion FD.
The reset transistor 23 is connected between a power supply line LVREF and the floating diffusion FD, and is to be given a reset signal RST to its gate through a reset control LRST.
Thus, the reset transistor 23 resets an electric potential of the floating diffusion FD to an electric potential of the power supply line LVDD.
The floating diffusion FD is connected with a gate of the amplifier transistor 24. The amplifier transistor 24 is connected to a signal line 26 (LSGN in FIG. 1) through the selection transistor 25, and constitutes a source follower with a constant current source outside a pixel section.
And, an address signal (a selection signal) SEL is to be given to the gate of the selection transistor 25 through a selection control line LSEL, and the selection transistor is turned on.
When the selection transistor 25 is turned on, the amplifier transistor 24 amplifiers the electric potential of the floating diffusion FD, and outputs voltage to the signal line 26. The voltage outputted by each pixel is to be outputted to the readout circuit 13 via the signal line 26.
This reset operation of pixels is to turn on the transfer transistor 22, and to transfer the electric charge accumulated in the photoelectric conversion element 21 to the floating diffusion FD, so as to output the electric charge accumulated in the floating diffusion FD.
At this time, the floating diffusion FD discards the electric charge to a side of power source by turning on the reset transistor 23 in advance so as to receive the electric charge of the photoelectric conversion element 21. Instead, it may discards the electric charge directly to the power source by turning on the reset transistor 23 in parallel while turning on the transfer transistor 22, in some cases.
To simplify these series of operation, it is called as “a pixel reset operation” or “a shutter operation”.
On the other hand, in a readout operation, at first, the reset transistor 23 is turned on to reset the floating diffusion FD, and via the selection transistor 25 which is turned on in the state, an output is performed to an output signal line 26. This is called as a P-phase output.
Subsequently, the transfer transistor 22 is turned on to transfer the electric charge accumulated in the photoelectric conversion element 21 to the floating diffusion FD, and its output is output to the signal line 26. This is called as D-phase output.
The difference between the D-phase output and the P-phase output outside of the pixel circuit to make it as an image signal, cancelling reset noise of the floating diffusion FD.
To simplify these series of operation, it is called simply as “a pixel readout operation”.
The transfer control line LTX, the reset control line LRST, and the selection control line LSEL are driven selectively by the vertical scan circuit 12.
As a structure of a pixel circuit, in addition to a four-transistor structure (4Tr-type) pixel circuit, it is possible to adapt a three-transistor structure (3Tr-type), a five-transistor structure (5Tr-type), or the like.
The above circuits are basic structures having the photoelectric conversion element in each pixel.
In addition, CMOS is also well-known for having a pixel section which has a pixel shared structure in which one selection control line, one reset control line, and a plurality of transfer control lines are arranged, and which includes a readout pixel section and an unread pixel section in the entirety.
One of features of CMOS image sensor having such structure is a function of random access to the pixel array section.
This realizes high-speed video that increases a frame rate by thinning necessary pixels to read out, a function for capturing determined region only to read out, or the like (for example, refer to Patent Literature 1).
FIG. 3 is a conceptual diagram for showing a structure of a CMOS image sensor which adapted a thinning and reading method, in case of 2 pixels shared.
This pixel section 11A shares, as shown in FIG. 3, the selection control line LSEL and the reset control line LRST, and two of the transfer control lines LTX1 and LTX2 are wired corresponding to two of photoelectric conversion elements, 21-1 (PD1) and 21-2 (PD2).
Before starting reading out, a reset state is set once, and after emptying the electrical charge left in the photoelectric conversion elements 21-1 and 21-2, next readout operation starts.
However, when reading out after thinning, if unread pixels are left as they are, there may be a possibility to cause blooming in which the electrical charge accumulated in the pixels leaks into the surroundings to be mixed with signals of the readout pixels.
To avoid this mixture of signals, the unread pixels also need to exclude the electrical charge from the pixels.
Various technologies have been provided for preventing occurrence of this blooming (for example, refer to Patent Literature 1).